Kaijie Wei - CLAHE implementation on a low-end FPGA board by

Journal article

Koki Honda, Kaijie Wei, Masatoshi Arai, H. Amano
2020 Eighth International Symposium on Computing and Networking Workshops (CANDARW), 2020

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APA Click to copy
Honda, K., Wei, K., Arai, M., & Amano, H. (2020). CLAHE implementation on a low-end FPGA board by high-level synthesis. 2020 Eighth International Symposium on Computing and Networking Workshops (CANDARW).

Chicago/Turabian Click to copy
Honda, Koki, Kaijie Wei, Masatoshi Arai, and H. Amano. “CLAHE Implementation on a Low-End FPGA Board by High-Level Synthesis.” 2020 Eighth International Symposium on Computing and Networking Workshops (CANDARW) (2020).

MLA Click to copy
Honda, Koki, et al. “CLAHE Implementation on a Low-End FPGA Board by High-Level Synthesis.” 2020 Eighth International Symposium on Computing and Networking Workshops (CANDARW), 2020.

BibTeX Click to copy

@article{koki2020a,
  title = {CLAHE implementation on a low-end FPGA board by high-level synthesis},
  year = {2020},
  journal = {2020 Eighth International Symposium on Computing and Networking Workshops (CANDARW)},
  author = {Honda, Koki and Wei, Kaijie and Arai, Masatoshi and Amano, H.}
}

Abstract

Automobile companies have been trying to replace side mirrors of cars with small cameras for reducing air resistance. It enables us to apply some image processing for improving quality. This paper describes a design of Contrast Limited Adaptive Histogram Equalization (CLAHE), which improves the quality of the dark image for the side mirror camera, on a low-end FPGA board by high-level synthesis. By constituting CLAHE as a data flow design flow, we could achieve performance comparable to the implementation with HDL. The code is parameterized so that the number of tiles and the size of the image can be easily changed. The source code for this research can be downloaded from https://github.com/kokihonda/fpga_clahe.