Kaijie Wei

Project Assistant Professor, Keio University

An implementation methodology for Neural Network on a Low-end FPGA Board


Journal article


Kaijie Wei, Koki Honda, H. Amano
International Symposium on Computing and Networking - Across Practical Development and Theoretical Research, 2020

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APA   Click to copy
Wei, K., Honda, K., & Amano, H. (2020). An implementation methodology for Neural Network on a Low-end FPGA Board. International Symposium on Computing and Networking - Across Practical Development and Theoretical Research.


Chicago/Turabian   Click to copy
Wei, Kaijie, Koki Honda, and H. Amano. “An Implementation Methodology for Neural Network on a Low-End FPGA Board.” International Symposium on Computing and Networking - Across Practical Development and Theoretical Research (2020).


MLA   Click to copy
Wei, Kaijie, et al. “An Implementation Methodology for Neural Network on a Low-End FPGA Board.” International Symposium on Computing and Networking - Across Practical Development and Theoretical Research, 2020.


BibTeX   Click to copy

@article{kaijie2020a,
  title = {An implementation methodology for Neural Network on a Low-end FPGA Board},
  year = {2020},
  journal = {International Symposium on Computing and Networking - Across Practical Development and Theoretical Research},
  author = {Wei, Kaijie and Honda, Koki and Amano, H.}
}

Abstract

Artificial Intelligence(AI) has achieved unprecedented success in various fields including image/speech recognition which is useful for edge computing. Most of AI systems are implemented on power-hungry devices like GPU, high-end FPGA, or even TPU to process data with high performance. However, these energy budgets are often not affordable to edge computing. Low-end FPGA taking advantage of high energy-efficiency is a desirable platform to meet the requirements of image recognition working on small autonomous vehicles. In this paper, we propose the design methodology and implementation to adapt a neural network system to a low-end FPGA board using HLS description.The whole design consists of algorithm-level downscaling and hardware optimization. The former emphasizes the model downscale by considering accuracy. The latter applies various HLS design techniques to speed-up the application running on the target board. In the case study of tiny YOLO (You Only Look Once) v3, the model running on PYNQ-Z1 presents up to 22× acceleration comparing with the PYNQ ARM CPU. Energy efficiency also achieves 3× better than Xeon E5-2667.