Kaijie Wei

Project Assistant Professor, Keio University

CLAHE Implementation and Evaluation on a Low-End FPGA Board by High-Level Synthesis


Journal article


Koki Honda, Kaijie Wei, Masatoshi Arai, H. Amano
IEICE Trans. Inf. Syst., 2021

Semantic Scholar DBLP
Cite

Cite

APA   Click to copy
Honda, K., Wei, K., Arai, M., & Amano, H. (2021). CLAHE Implementation and Evaluation on a Low-End FPGA Board by High-Level Synthesis. IEICE Trans. Inf. Syst.


Chicago/Turabian   Click to copy
Honda, Koki, Kaijie Wei, Masatoshi Arai, and H. Amano. “CLAHE Implementation and Evaluation on a Low-End FPGA Board by High-Level Synthesis.” IEICE Trans. Inf. Syst. (2021).


MLA   Click to copy
Honda, Koki, et al. “CLAHE Implementation and Evaluation on a Low-End FPGA Board by High-Level Synthesis.” IEICE Trans. Inf. Syst., 2021.


BibTeX   Click to copy

@article{koki2021a,
  title = {CLAHE Implementation and Evaluation on a Low-End FPGA Board by High-Level Synthesis},
  year = {2021},
  journal = {IEICE Trans. Inf. Syst.},
  author = {Honda, Koki and Wei, Kaijie and Arai, Masatoshi and Amano, H.}
}