Kaijie Wei

Project Assistant Professor, Keio University

RT-libSGM: An Implementation of a Real-time Stereo Matching System on FPGA


Journal article


Kaijie Wei, Yukinori Kuno, M. Arai, H. Amano
Heart, 2022

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APA   Click to copy
Wei, K., Kuno, Y., Arai, M., & Amano, H. (2022). RT-libSGM: An Implementation of a Real-time Stereo Matching System on FPGA. Heart.


Chicago/Turabian   Click to copy
Wei, Kaijie, Yukinori Kuno, M. Arai, and H. Amano. “RT-LibSGM: An Implementation of a Real-Time Stereo Matching System on FPGA.” Heart (2022).


MLA   Click to copy
Wei, Kaijie, et al. “RT-LibSGM: An Implementation of a Real-Time Stereo Matching System on FPGA.” Heart, 2022.


BibTeX   Click to copy

@article{kaijie2022a,
  title = {RT-libSGM: An Implementation of a Real-time Stereo Matching System on FPGA},
  year = {2022},
  journal = {Heart},
  author = {Wei, Kaijie and Kuno, Yukinori and Arai, M. and Amano, H.}
}

Abstract

Stereo depth estimation has become an attractive topic in the computer vision field. Although various algorithms strive to optimize the speed and the precision of estimation, the energy cost of a system is also an essential metric for an embedded system. Among these various algorithms, Semi-Global Matching (SGM) has been a popular choice for some real-world applications because of its accuracy-and-speed balance. However, its power consumption makes it difficult to be applied to an embedded system. Thus, we propose a robust stereo matching system, RT-libSGM, working on the Xilinx Field-programmable gate array (FPGA) platforms. The dedicated design of each module optimizes the speed of the entire system while ensuring the flexibility of the system structure. Through an evaluation running on a Zynq FPGA board called M-KUBOS, RT-libSGM achieves state-of-the-art performance with lower power consumption. Compared with the original design (libSGM), when working on the Tegra X2 GPU, RT-libSGM runs 2 × faster at a lower energy cost.